This invention generally relates to the manufacture of semiconductor devices, and more particularly, to a monitoring system for detecting and characterizing various classes of leakage in CMOS devices.
As the scaling of integrated circuit continues to progress, CMOS devices become prone to many different types of leakage problems. Current technology having a gate dielectric thinner than 10 nm, a channel length shorter than 50 nm, a junction depth thinner than 20 nm, the threshold voltage of fast devices below 200 mV are typically subject to serious leakage related problems.
Handling leakage problems has been profusely described in the art, as for instance, in U.S. Pat. No. 6,844,750 to Hsu et al. Therein is described a leakage monitoring apparatus that first measures die leakage and then generates digital keeper control bits to improve the performance of the dynamic circuits. More specifically, the sub-threshold leakage of CMOS devices on multiple locations of the die is simultaneously monitored. Based on the leakage information, keepers of dynamic circuits are properly sized to compensate for the leakage while maintaining the performance. The apparatus described uses a current mirror circuit to measure the sub-threshold leakage of pull down NMOS devices whose gates are connected to 150 mV. The patent is directed toward handling one specific class of circuit from being affected by sub-threshold leakage due to process variations. However, the apparatus described does not characterize other types of leakages, such as junction leakage, gate dielectric leakage. It neither addresses the problem of monitoring and quantifying the sub-threshold leakage of PMOS devices.
In another related patent, U.S. Pat. No. 6,844,771, issued to Chung-Hui Chen, there is described another class of leakage monitoring apparatus which first monitors the decoupling capacitor leakage voltage and selectively switches off any decoupling capacitor that displays a predetermined amount of leakage current. The apparatus detects the presence of gate dielectric leakage at a specific threshold level, i.e., when the leakage current multiplied by the gate resistance is smaller than ½ Vdd. When detected, a switch is triggered to shut off the capacitor. The proposed approach suffers from a serious problem, in that when the gate shows either a catastrophic failure or a broken gate oxide caused by pin-holes or other defects, the voltage drop exceeds a preset threshold level (e.g., ½ Vdd). As a result, the circuit fails to shut the decoupling capacitor off. Again, the cited patent is not suited for universal leakage characterization, since it makes no mention of how to measure other classes of leakage mechanisms other than capacitor leakage.
Gate Dielectric Leakage Characterization Circuit
As previously referred to, there are two classes of gate leakage: the first is known as normal leakage, while the second relates to the broken gate oxide leakage. The first class of leakage exhibits a weak temperature dependence and an activation energy value of approximately 0.4 eV. This value approximates the barrier height of the SiO2 to Si interface. A normal gate oxide leakage current of this class, also known as thermal emission current, is described in the article by C. R. Crowell and S. M. Sze, “Current Transport in Metal-Semiconductor Bafflers”, Solid State Electron, 1966, Vol. 9, p. 1035-1048. The leakage level ranges from 1aA to 1pA. The second class is a gate oxide leakage mechanism, commonly referred to as Fowler-Nordheim tunnel, and it, likewise, displays a weak temperature dependence. The leakage level ranges from 1 to 10 p{acute over (Å)}. This second class of leakage is caused by broken gate oxide on different substrates, and is characterized by a leakage current level ranging from 0.1 to 1 m{acute over (Å)}.
The behavior of an n-MOS and p-MOS capacitor abnormal leakage significantly differs from one another. Therefore, it becomes necessary that they be independently monitored and characterized. In general, the broken gate leakage of a p-MOS capacitor is known to display a two to three orders of magnitude higher leakage current level than that of an n-MOS capacitor.
Referring now to FIGS. 1A and 1B, a schematic diagram and a device cross-sectional view of an n-MOS capacitor leakage monitoring device is illustrated. The gate is attached to node “B1”, while the source, drain and body are connected to ground.
Referring to FIG. 2A and 2B, a schematic diagram and a device cross-sectional view of a PMOS capacitor leakage monitoring device are respectively shown. The gate is attached to node “B2”, while the source/drain and body are connected to the power supply.
Sub-Threshold Leakage Characterization Circuit
The sub-threshold characteristics of a MOSFET device have strong temperature dependence, i.e., the lower the temperature, the lower the leakage current. The sub-threshold leakage current is conventionally measured at Vg=0V or at any lower bias level, typically, of the order of about 150 mV.
Referring to FIGS. 3A and 3B, there are shown a schematic diagram accompanied by a device cross-section of an NMOS sub-threshold leakage monitoring device. The gate is connected to ground or biased at 150 mV, while the drain is attached to node “A1” and the source and body to ground.
Correspondingly, FIGS. 4A and 4B show a schematic diagram and a cross-sectional view of a p-MOS sub-threshold leakage monitoring device. The gate is connected to VDD or biased at (VDD-150 mV). The drain is shorted to node “A2” while the source and body are connected to VDD.
Junction Leakage Characterization Circuit
The reserve leakage current for a normal p-n junction displays a strong temperature dependence which is governed by the relationship exp(−Eg/kT), wherein Eg is the band-gap energy of the order of 1.1 eV. However, for an abnormal p-n junction, the leakage level is two to five orders of magnitudes higher than that of a normal device. Its activation energy remains below 0.1 eV.
Referring to FIGS. 5A and 5B, a schematic diagram and a device cross-sectional view of an NMOS reverse p-n junction leakage monitoring device are shown. The gate is connected to node “C1”, while the source, drain and body are attached to ground.
With reference to FIGS. 6A and 6B there are shown a schematic diagram and a device cross-sectional view of a p-MOS reverse p-n junction leakage monitoring device. The body is connected to node “C1”, while the gate, source and drain are connected to VDD.
It is conceivable that a single p-type or n-type CMOS device or a plurality of CMOS devices can be advantageously used for monitoring. By way of example, if the leakage is proportional to the size (also referred to as the width) of the device, one may use as many devices as the area allocated thereto permits it.
In summary, while the prior art has addressed the problem of measuring the sub-threshold leakage and how to generate feedback controls to maintain keeper strength of dynamic circuits, there still remains a problem of how to monitor the effect of different classes of leakages, such as gate leakage, junction leakage and device leakage across a chip.
Furthermore, while the prior art has provided means for measuring leakage in n-type devices, it has not been able to expand this teaching to other classes of CMOS devices, regardless whether p-type or n-type.
Finally, and referring to monitor circuits capable of achieving the aforementioned goals, they typically require complex and bulky circuitry, each monitor device requiring its own comparator, which are difficult to integrate in a CMOS fabrication facility.